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1 ps8959b 10/01/09 advance information - company confidential all trademarks are property of their respective owners. PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity features ? supply voltage, v dd = 3.3v 5% ? each of the three input ports can support hdmi? or dvi signals ? supports both ac-coupled and dc-coupled inputs ? supports deepcolor? ? high performance, up to 2.5 gbps per channel ? switching support for 3 side band signals (scl, sda and hpd) ? 5v tolerance on all side band signals ? scl, sda, and hpd pins are the only pins that can support hot insertion ? integrated 50-ohm (10%) termination resistors at each high speed signal input ? tmds input termination control on all high speed inputs ? hdcp reset circuitry for quick communication when switching from one port to another ? con gurable output swing control ? con gurable pre-emphasis levels ? con gurable de-emphasis ? optimized equalization single default setting will support all cable lengths ? 8kv contact esd protection on all input data/clock channels per iec61000-4-2 ? propagation delay 2ns ? high impedance outputs when disabled ? packaging (pb-free & green): ? 80-pin lqfp (ff80) ? 64-pin tqfn (zl64) description pericom semiconductor?s PI3HDMI301 3:1 active switch circuit is targeted for high-resolution video networks that are based on dvi/hdmi? standards and tmds signal processing. the PI3HDMI301 is an active 3 tmds to 1 tmds receiver switch with hi-z outputs. the device receives differential signals from selected video components and drives the video display unit. it provides controllable output swings, as well as provides a unique advanced pre-emphasis technique to increase rise and fall times which are reduced during transmission across long distances. each complete hdmi/dvi channel also has slower speed, side band signals, that are required to be switched. pericom?s solution provides a complete solution by integrating the side band switch together with the high speed switch in a single solution. using equalization at the input of each of the high speed channels, pericom can successfully eliminate deterministic jitter caused by long cables from the source to the sink. the elimination of the deterministic jitter allows the user to use much longer cables (up to 25 meters). the maximum dvi/hdmi bandwidth of 2.5 gbps provides 36-bit deep color? support, which is offered by hdmi? revision 1.3. due to its active uni-directional feature, this switch is designed for usage only for the video receiver?s side. for consumer video networks, the device sits at the receiver?s side to switch between multiple video components, such as pc, dvd, stb, d-vhs, etc. the PI3HDMI301 also provides enhanced robust esd/eos protection of 8kv, which is required by many consumer video networks today. the optimized equalization provides the user a single optimal setting that can provide passing results for hdmi jitter tests for all cable lengths: 1meter to 20meters with deepcolor support up to 36bits. pericom also offers the ability to ne tune the equalization settings in situations where cable length is known. for example, if 25meter cable length is required, pericom's solution can be adjusted to 16db eq to accept 25meter cable length. 09-0054
2 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. pin con guration (top view) 1 23 45 6 7 8 9 10 11 12 13 14 1516 1718 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 eq_s1 gnd eq_s0 d2+3 d2-3 vdd d1+3 d1-3 gnd d0+3 d0-3 vdd clk+3 clk-3 gnd scl3 sda3 hpd3 vdd oe oc_s3 sda1 oc_s2 scl1 gnd clk-1 clk+1 vdd d0-1 d0+1 gnd d1-1 d1+1 vdd d2-1 d2+1 gnd vdd oc_s1 oc_s0 vdd hpd2 hpd1 sda2 scl2 gnd gnd clk-2 clk+2 vdd d0-2 d0+2 gnd d1-2 d1+2 vdd d2-2 d2+2 gnd vdd hpd_sink sda_sink s2 scl_sink gnd gnd clk- clk+ vdd d0- d0+ gnd d1- d1+ vdd d2- d2+ gnd s3 s1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 s1 s2 s3 d2+ d2C vdd d1+ d1C d0+ d0C vdd clk+ clkC scl_sink sda_sink hpd_sink sda1 scl1 clkC1 clk+1 vdd d0C1 d0+1 d1C1 d1+1 vdd d2C1 d2+1 vdd oc-s1 oc_s0 oc_s2 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 d2+3 d2C3 vdd d1+3 d1C3 d0+3 d0C3 vdd clk+3 clkC3 scl3 sda3 hpd3 vdd oe eq_s0 oc_s3 hpd1 d2+2 d2C2 vdd d1+2 d1C2 d0+2 d0C2 vdd clk+2 clkC2 scl2 sda2 hpd2 eq_s1 gnd (top view) 09-0054
3 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. receiver block 1 clk+/-, dx+/- r2 250kohm r1 avdd each input has integrated equalization that can eliminate deterministic jitter caused by 25meter 24awg cables. all activity can be con gured using pin strapping. the rx block is designed to receive all relevant signals directly from the hdmi tm connec- tor without any additional circuitry, 3 high speed tmds data, 1 pixel clock, 1 hpd signals, and ddc signals. tmds channels have following termination scheme for rx sense support. note: 1. r 1 + r 2 = 50 ? 09-0054
4 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. pin description 80 lqfp pin # 64 tqfn pin # pin name i/o description 9, 12, 15, 6 7, 9,12, 4 d 0 +1, d 1 +1, d 2 +1, clk+1 i port 1 tmds positive inputs 71, 74, 77, 68 57, 59, 62, 54 d 0 +2, d 1 +2, d 2 +2, clk+2 i port 2 tmds positive inputs 52, 55, 58, 49 43, 45, 48, 40 d 0 +3, d 1 +3, d 2 +3, clk+3 i port 3 tmds positive inputs 8, 11, 14, 5 6, 8, 11, 3 d 0 -1, d 1 -1, d 2 -1, clk-1 i port 1 tmds negative inputs 70, 73, 76, 67 56, 58, 61, 53 d 0 -2, d 1 -2, d 2 -2, clk-2 i port 2 tmds negative inputs 51, 54, 57, 48 42, 44, 47, 39 d 0 -3, d 1 -3, d 2 -3, clk-3 i port 3 tmds negative inputs 4, 10, 16, 24, 30, 36, 37, 47, 53, 59, 65, 66, 72, 78 gnd ground 80 63 hpd1 o port 1 hpd output 62 50 hpd2 o port 2 hpd output 44 36 hpd3 o port 3 hpd output 40 32 hpd_sink i sink side hot plug detector input. high: 5-v power signal asserted from source to sink and edid is ready. low: no 5-v power signal asserted from source to sink, or edid is not ready. 42 34 oe i output enable, active low 3 2 scl1 i/o port 1 ddc clock 64 52 scl2 i/o port 2 ddc clock 46 38 scl3 i/o port 3 ddc clock 38 31 scl_sink i/o sink side ddc clock 2 1 sda1 i/o port 1 ddc data 63 51 sda2 i/o port 2 ddc data 45 37 sda3 i/o port 3 ddc data 39 31 sda_sink i/o sink side ddc data 21, 22, 23 17, 18, 19 s1, s2, s3 i source input control 7, 13, 17, 27, 33, 43, 50, 56, 61, 69, 75, 79 5, 10, 22, 27, 35, 41, 46, 55, 60 v dd 3.3v power supply 31, 28, 25, 34 25, 23, 20, 28 d 0 +, d 1 +, d 2 +, clk+ o tmds positive outputs 32, 29, 26, 35 26, 24, 21, 29 d 0 -, d 1 -, d 2 -, clk- o tmds negative outputs 41, 60 33, 49 eq_s0, eq_s1 i equalizer controls, both controls have internal pull-ups 19, 18, 20, 1 15, 14, 16, 64 oc_s0, oc_s1, oc_s2, oc_s3 i output buffer controls, all control bits have internal pull-ups 09-0054
5 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. switch block diagram r e v i e c e r q e h t i w r e v i e c e r q e h t i w r e v i e c e r q e h t i w r e v i e c e r q e h t i w r e v i e c e r q e h t i w r e v i e c e r q e h t i w r e v i e c e r q e h t i w dd v r e v i e c e r q e h t i w control logic 3-to-1 mux tdms drive tdms drive tdms drive tdms drive . . . . . . hpd1 hpd2 d0+ d0- d1+ d1- d2+ d2- clk+ clk- oe s1 hpd_sink scl_sink scl1 sda1 scl2 sda2 sda_sink oc_s1 oc_s2 oc_s3 eq_s1 oc_s 0 eq_s 0 r2 r2 250k dd v r2 r2 250k dd v r2 r2 250k dd v r2 r2 250k dd v r2 r2 250k dd v r2 r2 250k dd v r2 r2 250k dd v r2 r2 250k r e vi ec er qe hti w r e vi ec er qe hti w r e vi ec er qe hti w r e vi ec er qe hti w . . . d0+3 d0-3 d1+3 d1-3 d2+3 d2-3 dd v r2 r2 250k dd v r2 r2 250k dd v r2 r2 250k dd v r2 r2 250k 09-0054
6 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. oc setting value logic table 0 input control pins setting value oc_s3 (1) oc_s2 (1) oc_s1 (1) oc_s0 (1) vswing (mv) pre-emphasis/de-emphasis (db) 0 0 0 0 333 -9.5 0 0 0 1 500 -6 0 0 1 0 666 -3.5 0 0 1 1 1000 0 0 1 0 0 160 -9 0 1 0 1 270 -6 0 1 1 0 340 -3.5 0 1 1 1 500 0 1 0 0 0 500 6 1 0 0 1 500 3.5 1 0 1 0 500 1.5 1 0 1 1 500 0 1 1 0 0 600 0 1 1 0 1 1000 0 1 1 1 0 750 0 1 1 1 1 500 0 eq setting value logic table for high speed data bits (tmds clk input is left at 3db default always) eq_s1 (1) eq_s0 (1) setting value 0 0 15db on all high speed data inputs 0 1 3db on all high speed data inputs 1 0 8db on all high speed data inputs 1 1 optimized equalization on all high speed data inputs (default setting which can support all cable lengths from 1meter to 20meters) notes: 1) integrated internal pull-ups truth table control pins i/o selected hot plug detect status oe s1 s2 s3 tmds outputs scl_sink sda_sink hpd1 hpd2 hpd3 l h x x port1 scl1 sda1 hpd_sink l l l l h x port2 scl2 sda2 l hpd_sink l l l l h port3 scl3 sda3 l l hpd_sink l l l l none (hi-z) none (hi-z) l l l h x x x none (hi-z) follow s1, s2, s3 follow s1, s2, s3 09-0054
7 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. storage temperature .................................................... ?65c to +150c supply voltage to ground potential ................................ ?0.5v to +4.0v dc input voltage ...............................................................?0.5v to v dd dc output current ....................................................................... 120ma power dissipation ........................................................................... 1.0w note: stresses greater than those listed under max i mum rat ings may cause permanent damage to the de vice. this is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i ca tion is not implied. exposure to ab- solute max i mum rating con di tions for extended periods may affect re li abil i ty. maximum ratings (above which useful life may be impaired. for user guide lines, not tested.) recommended operating conditions symbol parameter min. typ. max. units v dd supply voltage 3.135 3.3 3.465 v t a operating free-air temperature 0 70 c tmds differential pins v id receiver peak-to-peak differential input voltage 150 1560 mvp-p v ic input common mode voltage 2 v dd + 0.01 v v dd tmds output termination voltage 3.135 3.3 3.465 v r t termination resistance 45 50 55 ohm signaling rate 0.25 2.5 gbps control pins (oc_sx, eq_sx, sx, oe) v ih lvttl high-level input voltage 2 v dd v v il lvttl low-level input voltage gnd 0.8 ddc pins (sclx, scl_sink, sdax, sda_sink) v i(ddc) input voltage gnd 5.5 v status pins (hpd_sink) v ih lvttl high-level input voltage 2 5.3 v v il lvttl low-level input voltage gnd 0.8 09-0054
8 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. item hdmi tm 1.3 spec pericom product spec operating conditions termination supply voltage, v dd 3.3v 5% 3.30 5% terminal resistance 50-ohm 10% 45 to 55-ohm source dc characteristics at tp1 single-ended high level output voltage, vh v dd 10mv v dd 10mv single-ended low level output voltage, vl ( v dd - 600mv) vl ( v dd - 400mv) ( v dd - 600mv) vl ( v dd - 400mv) single-ended output swing voltage, vswing 400mv vswing 600mv 400mv vswing 600mv single-ended standby (off) output voltage, voff v dd 10mv v dd 10mv transmitter ac characteristics at tp1 risetime/falltime (20%-80%) 75ps risetime/falltime 0.4 tbit (75ps tr/tf 242ps) @ 1.65 gbps 240ps intra-pair skew at transmitter connector, max 0.15 tbit (90.9ps @ 1.65 gbps) 60ps max inter-pair skew at transmitter connector, max 0.2 tpixel (1.2ns @ 1.65 gbps) 100ps max clock jitter, max 0.25 tbit (151.5ps @ 1.65 gbps) 82ps max sink operating dc characteristics at tp2 input differential voltage level, vdiff 150 vdiff 1200mv 150mv v diff 1200mv input common mode voltage level, v icm ( v dd - 300mv) vicm ( v dd -37.5mv) or v dd 10% ( v dd - 300mv) vicm ( v dd -37.5mv) or v dd 10% sink dc characteristics when source disabled or disconnected at tp2 differential voltage level v dd 10mv v dd 10mv tmds compliance test results 09-0054
9 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. electrical characteristics (over recommended operating conditions unless otherwise noted) symbol parameter test conditions min. typ. (1) max. units i cc supply current v ih = v dd , v il = v dd - 0.4v, r t = 50-ohm, v dd = 3.3v data input = 1.65 gbps hdmi tm data pattern clk input = 165 mhz clock 200 ma p d power dissipation 660 mw i ccq standby current oe = high, s1 = s2 = s3 = low 8 ma tmds differential pins v oh single-ended high-level output voltage v dd = 3.3v, r t = 50-ohm pre-emphasis/de-emphasis = 0db v dd - 10 v dd + 10 mv v ol single-ended low-level output voltage v dd - 600 v dd - 400 v swing single-ended output swing voltage 400 600 v od(o) overshoot of output differential voltage 6% 15% 2x v swing v od(u) undershoot of output differential voltage 12% 25% v oc(ss) change in steady-state common- mode output voltage between logic states 0.5 5 mv |i (os) | short circuit output current 12 ma v ode(ss) steady state output differential voltage oc_sx = gnd, data input = 250 mbps hdmi tm data pattern clk input = 25 mhz clock x = 0, 1, 2, 3 560 840 mvp-p v ode(pp) peak-to-peak output differential voltage 800 1200 v i(open) single-ended input voltage under high impedance input or open input i i = 10a v dd - 10 v dd + 10 mv r int input termination resistance v in = 2.9v 45 50 55 ohm ddc i/o pins (sclx, scl_sink, sdax, sda_sink) |i lkg | input leakage current v i = 5.5v -50 50 a v i = v dd -10 10 c io input/output capacitance v i = 0v 7.5 pf r on switch resistance i o = 3ma, v o = 0.4v 25 50 ohm v pass switch output voltage v i = 3.3v, i i = 100a 1.5 (2) 2.0 2.5 (3) v status pins (hpd) v oh(ttl) ttl high-level output voltage i oh = -4ma 2.4 v v ol(ttl) ttl low-level output voltage i ol = 4ma 0.4 v (table continued) 09-0054
10 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. symbol parameter test conditions min. typ. (1) max. units control pins (oc_sx, eq_sx, sx, oe) i ih high-level digital input current v ih = 2.0v or v dd -10 10 a i il low-level digital input current v il = gnd or 0.8v -10 10 status pins (hpd_sink) i ih high-level digital input current v ih = 5.3v -50 50 a v ih = 2.0v or v dd -10 10 i il low-level digital input current v il = gnd or 0.8v -10 10 electrical characteristics (continued) notes: 1. all typical values are at 25 c and with a 3.3v supply. 2. the value is tested in full temperature range at 3.0v. 3. the value is tested in full temperature range at 3.6v. 09-0054
11 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. switching characteristics (over recommended operating conditions unless otherwise noted) symbol parameter test conditions min. typ. (1) max. units tmds differential pins tpd propagation delay v dd = 3.3v, r t = 50-ohm, pre-emphasis/de-emphasis = 0db 2000 ps t r differential output signal rise time (20% - 80%) 75 140 t f differential output signal fall time (20% - 80%) 75 140 t sk(p) pulse skew 10 50 t sk(d) intra-pair differential skew 23 50 t sk(o) inter-pair differential skew (2) 100 tclk jit(pp) peak-to-peak output jitter from tmds clk channel residual jitter pre-emphasis/de-emphasis = 0db, data input = 1.65 gbps hdmi tm data pattern clk input = 165 mhz clock 15 30 tdata jit(pp) peak-to-peak output jitter from tmds data residual jitter 18 50 t de de-emphasis duration de-emphasis = -3.5db, data input = 250 mbps hdmi tm data pattern, clk input = 25 mhz clock 240 t sx select to switch output 10 ns t en enable time 200 t dis disable time 10 ddc i/o pins (sclx, scl_sink, sdax, sda_sink) t pd(ddc) propagation delay from scln to scl_sink or sdax to sda_sink or sda_sink to sdax c l = 10pf 0.4 2.5 ns control and status pins (oc_sx, eq_sx, sx, hpd_sink, hpdx) t pd(hpd) propagation delay (from hpd_sink to the active port of hpdx) c l = 10pf 2 6.0 ns t sx(hpd) switch time (from port select to the latest valid status of hpdx) 3 6.5 notes: 1. all typical values are at 25 c and with a 3.3v supply. 2. t sk(o) is the magnitude of the difference in propagation delay times between any speci ed terminals of channel 2 to 4 of a device when inputs are tied together. application information supply voltage all v dd pins are recommended to have a 0.01 f capacitor tied from v dd to gnd to lter supply noise tmds inputs standard tmds terminations have already been integrated into pericom?s PI3HDMI301 device. therefore, external terminations are not required. any unused port must be left oating and not tied to gnd. 09-0054
12 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. tmds output oscillation elimination the tmds inputs do not incorporate a squelch circuit. therefore, we reccomend the input to be externally biased to prevent output oscillation. one pin will be pulled high to v dd with the other grounded through a 1.5k-ohm resistor as shown. tmds input fail-safe recommendation s s s s r t r t av cc v dd tmds tmds driver receiver r int r int 1.5kohm 09-0054
13 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. recommended power supply decoupling circuit figure 1 is the recommended power supply decoupling circuit con guration. it is recommended to put 0.1 f decoupling capacitors on each v dd pins of our part, there are four 0.1 f decoupling capacitors are put in figure 1 with an assumption of only four v dd pins on our part, if there is more or less v dd pins on our pericom parts, the number of 0.1 f decoupling capacitors should be adjust- ed according to the actual number of v dd pins. on top of 0.1 f decoupling capacitors on each v dd pins, it is recommended to put a 10 f decoupling capacitor near our part?s v dd , it is for stabilizing the power supply for our part. ferrite bead is also recommended for isolating the power supply for our part and other power supplies in other parts of the circuit. but, it is optional and depends on the power supply conditions of other circuits. figure 1 recommended power supply decoupling circuit diagram pericom part vdd vdd vdd vdd from main power supply 0.1f 0.1f 0.1f 0.1f ferrite bead 10f 09-0054
14 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. requirements on the decoupling capacitors there is no special requirement on the material of the capacitors. ceramic capacitors are generally being used with typically materi- als of x5r or x7r. layout and decoupling capacitorplacement consideration i. each 0.1 f decoupling capacitor should be placed as close as possible to each v dd pin. ii. v dd and gnd planes should be used to provide a low impedance path for power and ground. iii. via holes should be placed to connect to v dd and gnd planes directly. iv. trace should be as wide as possible v. trace should be as short as possible. vi. the placement of decoupling capacitor and the way of routing trace should consider the power owing criteria. vii. 10f capacitor should also be placed closed to our part and should be placed in the middle location of 0.1 f capacitors. viii. avoid the large current circuit placed close to our part; especially when it is shared the same v dd and gnd planes. since large current owing on our v dd or gnd planes will generate a potential variation on the v dd or gnd of our part. figure 2 layout and decoupling capacitor placement diagram pericom part gnd plane v dd plane 0.1uf bypass noise power flow 09-0054
15 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. package mechanical: 80-pin, low pro le quad flat package (ff80) description: 80-contact, low pro le quad flat package (lqfp) package code: ff (ff80) document control #: pd-2064 revision: a date: 03/18/09 07-0100 top view: note: ? for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 09-0054
16 ps8959b 10/01/09 PI3HDMI301 3:1 active switch for hdmi? signals with optimized equalization for enhanced signal integrity advance information - company confidential all trademarks are property of their respective owners. pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com ordering information ordering code package code package description PI3HDMI301ffe ff 80-pin, pb-free & green lqfp PI3HDMI301zle zl 64-pin, pb-free & green tqfn notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free and green ? adding an x suf x = tape/reel package mechanical: 64-pin, quad flat package (zl64) n f q t , d a e l - o n t a l f d a u q h c t i p e n i f n i h t , t c a t n o c - 4 6 : n o i t p i r c s e d l z : e d o c e g a k c a p 7 6 0 2 - d p : # l o r t n o c t n e m u c o d b : n o i s i v e r 10/28/08 : e t a d 08-0530 top view: bottom view: note: ? for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 09-0054

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